MOSFETs, and classical and quantum mechanical approaches in MOS characterization

Metal insulator semiconductor (MIS) or specifically metal oxide semiconductor (MOS) capacitors are the building blocks of today's integrated circuit technology (IC). Although, the first bipolar transistor (BJT) was invented serendipitously in 1948, Metal oxide semiconductor field effect transistors (MOSFETs, first demonstrated in 1960) have supplanted BJTs in almost all logic applications. BJTs are still the first choice when high current densities are required.

To understand the working principle of BJTs and MOSFET, one should know what a p-n junction is and how it behaves under different bias conditions. This topic, as well as an introduction to MOSFETs, are covered by Maria. Therefore, here, working principle of a MOSFETs is briefly summarized from the viewpoint of band diagrams.

MOSFET is an active device with (at least) 3 terminals. It can be considered as a variable resistor (resistor between source and drain) which has a very large resistance when it is off. Channel resistance can be tuned by the gate voltage. Figure 1 shows cross section of an n-channel MOSFET (NMOS), energy band diagram along the channel and ID-VD (output) characteristics. When the gate voltage is zero, channel can be normally on or off depending on the doping concentrations of source/drain and the body (substrate). If a device is on by default, it is called depletion mode device. Otherwise it is in enhancement mode, which requires additional positive bias on the gate to turn on the device (for an NMOS device). Energy band diagram of the MOSFET given in Figure 1, shows that electrons in drain and source region see a barrier in the middle (p-type body), where holes in the body also experience barriers in the valence band of source and drain regions. Total current from the drain to source (or electron flow from source to drain ), therefore, is very small (only leakage current). However, when a positive bias applied on the gate barrier in the middle lowers, which in turns increases the drain to source current (ID). Minimum voltage level that needs to be applied on gate in order to get significant ID is called as threshold voltage (VTH). ID-VD curves of this device show a linear behavior followed by a saturation region. Saturation current level increases with increased gate bias. Although, an NMOS device is discussed here, same working principles apply on a PMOS device with opposite carrier types and reversed voltage biases.

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Figure 1. (Top) Cross section of an NMOS device, and corresponding energy-band diagram. (Bottom) ID-VD characteristics of the device for different gate bias conditions [1].

ID-VD characteristics of MOSFETs can be derived in a similar way done for p-n junctions. Drain current (ID) as a function of gate (VG) and drain (VD) biases are given as following:

\begin{align} I_{D} = \frac{\mu ZC_{i}}{L}[(V_{G}-V_{TH})V_{D})-\frac{1}{2}V_{D}^{2}] \end{align}

where $\mu$ is the mobility of carriers in the channel (significantly degraded compared to bulk value), Z is the channel width, Ci is the insulator capacitance per area (F/m2) and L is the channel length. When the device is on, it is desirable to have large current and ideally when it is off, the current (leakage current) should be very small. In order to have large on-current, one (or combination) of followings can be done: scaling the channel length down, mobility enhancement, widening the channel width or increasing the insulator capacitance. Silicon MOSFETs have been scaled down to 32 nm gate length (will be in market soon by Intel) which provides very fast devices with very high packaging density following scaling down trend. However, scaling down the devices comes with its drawbacks (short channel effects).

MOS capacitor characterization is vital for electrical analysis of MOSFET devices. Capacitance-Voltage (CV) analysis is another important parameter for MOSFET characterization together with its output (ID-VD) and transfer (ID-VG)characteristics. MOS capacitor is formed by metal, insulator (oxide) and a semiconductor junction (for simplicity drain and source regions are not introduced in the semiconductor region). This system can be assumed to be a parallel plate capacitor with a capacitance of:

\begin{align} C = \epsilon \frac{A}{t} \end{align}

where $\epsilon$ is the dielectric constant of the oxide, A is the cross section are and t is the oxide thickness. Since we are interested in capacitance of unit area, defining $C_{i} = \frac{\epsilon}{t}$ makes more sense. From the Eq. 1, increase in Ci gives rise to increase in ID. However, in order to increase Ci , oxide thickness should be scaled down which yields to increased gate current leakage (undesired). Therefore, high-k dielectric has been a hot topic as the MOSFET devices scale down (Intel has introduced high-k HfO2 - Hf stack last year (2007)). Energy band diagrams of a n-MOS capacitor with different bias conditions are given in Figure 2.

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Figure 2. (a) Flat band condition. (b) Majority carrier accumulation. (c) Depletion of majority carriers. (d) Inversion of the channel (minority carriers are attracted to semiconductor-oxide interface) [1].

Figure 2a shows a flat band condition of the the MOS capacitor, where metal's and semiconductor's work function are same (for more understanding of work functions, please see Dharma's page). When a negative bias is applied on the gate (Figure 2b), energy of the metal increases resulting into tilt in oxide and bending in the semiconductor. Since the semiconductor is p-type (majority carriers are holes), holes will accumulated at the semiconductor-oxide interface (holes are like bubbles, they want to go up in energy band diagrams). Applied voltage potential splits the fermi level of metal and the semiconductor. Figure 2c shows the band diagram when a small positive bias is applied on the gate. Positive bias on the gate repels the holes in the semiconductor which results in a depletion region. Further increase in positive bias attracts electrons (minority carriers) at the junction, in other words p-type semiconductor behaves like an n-type (inverted) at the junctions. Charge distribution, electric field and voltage potential of this system in inversion are given in Figure 3.

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Figure 3. Energy-band diagram of a MOS capacitor in inversion and corresponding charge distribution, electric field and voltage potential [1].

Since negatively charged inversion carriers and ionized dopants are left behind in the semiconductor, opposite charge will appear in the metal just at the interface. Interface charge appears as a sharp peak (exaggerated for illustration purposes ), where ionized dopants are more uniformly distributed in the semiconductor. Capacitance of this system determined by the dielectric constant and thickness of the oxide. Classical approach assumes that all the inversion layer is just at the interface, however due to electron confinement in the channel, electron distribution has to be calculated by solving the Schrodinger's equation.

Quantum mechanical approach requires solving Poisson's and Schrodinger's equations (Eq. 3) in the quantum well. 2-D well is assumed to be triangular. This approximation holds for region very close to Si-SiO2 interface, although it deviates from its linear behavior away from the oxide-semiconductor interface.

\begin{align} -\frac{h^{2}}{2\pi m}\frac{d^{2}\psi (x)}{dx^{2}}+qV(x)\psi (x)=E\psi (x) \end{align}

where V(x) is linear function of x in the semiconductor and $\propto$ just at the oxide interface. Solution to this differential equation is Airy functions with eigenvalues of:

\begin{align} E_{j}=[\frac{3hq\varepsilon_{s}}{4\sqrt{2m_{x}}\frac{}{}}(j+\frac{3}{4})) ]^{2/3} \end{align}

where $\varepsilon_{s}$ is the electric field in the well, and mx is the effective mass of electrons. Resulting wave function for the lowest energy level is given in Figure 4.

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Figure 4. Energy band diagram of the inverted semiconductor and resulting wave function in the lowest energy level [2].

I want to conclude this paper with practical results of this quantum mechanical effect on MOS capacitors:

- Minority carrier concentration peaks away from the interface, as opposed to classical approach.
- Threshold voltage increases as this quantum mechanical effect dominates (at high fields) due to increased distance between the gate and the channel.
- Electrons occupy discrete levels of energy, rather than bottom of the conduction band at the interface.
- Carriers are affected less by the interface scatterings.

[1] B. G. Streetman, Solid State Electronic Devices. ,6th ed.Prentice Hall, 2006.
[2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge University Press New York, NY, USA, 1998.

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